Bias Stability

An unexplained bias distortion invariably beginning at the start of a science run and enduring for hundreds of readout frame times has resulted in much consternation over worthless data and the current implementation of the prophylactic regimen with the charming sobriquet "jitter-dacs" which has become a permanent feature of the flight software. The distortion is clearly produced by an excess of charge which only accrues when the parallel clock low level does not go below some near 0 volt level for a period of time equal to or greater than a single frame readout cycle. It is possible to believe that the sources of the charge are surface states lying directly under the gates, or at the gate-silicon junctures. Bringing the gate voltage low (or more precisely, jittering the voltage many times between high and low) depletes these states once and for all time. While this may be difficult to believe it is indisputable that without jitter-dacs neither useful data or bias can be acquired for a long time after the start of a science run.

It should be noted that apparent bias instabilities have occasionally been observed after the installation of the ``jitter-dacs'' feature in the ACIS flight software. One such example, alluded to in section 4.7.3 occurred in ACIS XRCF Science Run 93 (TRW ID's I-IAS-SG-1.032 and I-IAS-EA-2.043 through I-IAS-EA-2.048) and affected the bias of detector S4. The cause of this instability is unknown. It may be relevant that S4 is unique among ACIS detectors in having framestore parallel clock levels equal to the imaging area clock levels at (+2,+11V). All other detectors have framestore clock levels of (-4.5,+5V).