Effects of Parallel Register Clock Levels on Detection Efficiency

The clock voltages in the image section of a CCD determine the depletion depth of the device. The more positive both levels (low and high) are, the bigger is the depletion depth and, hence, the high energy quantum efficiency. For this reason the standard levels were chosen to be as high as they can safely be, namely, +11 Volts being the high level and +2 Volt the low level. An attempt to further increase the high level voltage above +12 Volts resulted in an increased dark current due to avalanche multiplication of electrons in the channel (so-called ``spurious charge'' effect). In order to reduce dark current in the frame store section the low clock level there is set to -4.5 Volts. This keeps the surface of silicon under nonintegrating gates in inverted mode, thus suppressing surface generation centers. With the standard levels (+2,+11 Volts) in the image section the depletion depth of the devices varies around a typical value of 70 microns.

For each of the flight devices a measurement was also made with reduced clock levels in the image section. The voltges were chosen to keep nonintegrating gates in inversion with the clock levels at -4.5 and +5 Volts. During calibration the devices did not show any difference in the dark current for the two modes. But the reduced level mode may prove useful when a device undergoes irradiation in space and the level of dark current goes up. The drawback of reducing image clock levels is a reduced depletion depth and, consequently, reduced quantum efficiency at energies above 4 keV. The depletion depth of each flight device was measured in both modes, and results can be found in the Table 4.30 of Section 4.6.2.

In Fig. 4.96 is shown a calculated ratio of quantum efficiencies for the device w193c2 in two different modes. The measured depletion depths for the two modes were found to be 65 and 48 microns, respectively, for standard and reduced voltages. Based on these numbers quantum efficiency was calculated for each mode.

Figure 4.96: The ratio of quantum efficiencies for the devide w193c2 with the standard clock levels and the reduced clock levels.