The ICP (Image & Control Processor) board is based on a NEC V30 microprocessor running at 10 MHz. Laboratory tests of the event recognition algorithm running on 8086 and 80386 machines and processing real CCD frames indicate that our design can process the expected event rates with a comfortable margin.
The software for the ICP board is stored in Seeq DM28C256 32K 
8 EEPROMs. The EEPROMs have been purchased and subjected to radiation
testing with 
Co by D. Chornay of GSFC. The EEPROMs were tested
up to 30 krads without failure (this is far in
excess of expected dose on orbit). On boot or reset, the software
will be downloaded from the EEPROMs into static RAM and the EEPROMs
will be powered down while the ICP runs from RAM.
A variety of static RAMs were tested by 
Co irradiation at GSFC.
Based on these tests, we selected Samsung KM681000LP-8 devices for our
design. The ICP board incorporates 2 Mbytes of static RAM
for the science memory plus
1 Mbyte of ECC (Error Correction Code) memory.
The ECC codes allow correction of all single bit
errors and identification of all 2 bit and some 3 bit errors.
Error correction will
be performed on the ground during data processing, rather than on-board.
In addition to collecting science and housekeeping data, identifying events, formatting data for telemetry, and processing commands from the ground, the ICP board is able to perform self-tests and other functions.